Semiconductor device and method of manufacturing the same

ABSTRACT

Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-113570, filed Apr. 16,2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and asemiconductor device manufacturing method and, more particularly, to athermal annealing technology.

2. Description of the Related Art

High integration of LSIs has been achieved by reducing sizes of elementsconstructing LSIs. With decreasing dimensions of elements, the formationof a shallow p-n junction, i.e., the formation of a shallow impuritydiffusion region is becoming important.

To form this shallow impurity diffusion region, ion implantation at lowacceleration energy and optimization of subsequent annealing areimportant. Boron (B) is used as a p-type impurity, and phosphorus (P)and arsenic (As) is used as an n-type impurity. However, theseimpurities have larger diffusion coefficients in silicon (Si).Therefore, these impurities diffuse inward and outward when RTA (RapidThermal Anneal) using a halogen lamp is performed. This gradually makesit difficult to obtain a shallow impurity diffusion layer. If theannealing temperature is lowered to suppress impurity diffusion, theactivation ratio of the impurity largely decreases. By RTA using ahalogen lamp, therefore, it is difficult to form an impurity diffusionlayer having a shallow (about 20 nm or less) junction and lowresistance.

To solve the above problem, a flash lamp annealing method using a xenon(Xe) flash lamp is being studied as a method of momentarily supplyingenergy required for activation. A Xe flash lamp is obtained by sealingXe gas in a tube such as a quartz tube. This Xe flash lamp can emitwhite light within the range of, e.g., a few 100 μsec to a few msec bydischarging electric charge stored in a capacitor within a short timeperiod. Accordingly, an impurity can be activated without changing thedistribution of impurity ions implanted into a semiconductor layer.

Unfortunately, the light of the flash lamp is reflected by the surfaceof a semiconductor substrate to worsen the heating efficiency. Thismakes sufficient impurity activation difficult. If the irradiationenergy of the flash lamp is increased to raise the activation ratio, thethermal stress increases, and this destroys the semiconductor substrate.That is, the conventional flash lamp annealing method can form animpurity diffusion region having a shallow junction but cannotunlimitedly lower the resistance of the diffusion layer.

Another conventional technique known to those skilled in the art is toform a light-absorbing film to efficiently absorb lamp light duringannealing. Jpn. Pat. Appln. KOKAI Publication No. 10-26772 discloses atechnique which forms a light-absorbing film on the surface of a gateinsulating film in the fabrication of a TFT (Thin Film Transistor).Since, however, the light-absorbing film formed on the surface of a gateinsulating film is used, efficient heating is difficult to perform. Jpn.Pat. Appln. KOKAI Publication No. 2000-138177 discloses a techniquewhich forms a light-absorbing film on the surface of an interlayerinsulating film in the fabrication of a semiconductor device. However,the use of the light-absorbing film formed on the surface of aninterlayer insulating film also makes efficient heating difficult.

As described above, as the integration degree of LSIs increases, it isbecoming important to control the impurity profile with high accuracy,e.g., to form a shallow, low-resistance impurity diffusion layer.However, accurately controlling the impurity profile is conventionallydifficult.

BRIEF SUMMARY OF THE INVENTION

A first aspect of the present invention is a method for manufacturing asemiconductor device comprising: implanting ions of an impurity elementinto a semiconductor region; implanting, into the semiconductor region,ions of a predetermined element which is a group IV element or anelement having the same conductivity type as the impurity element andlarger in mass number than the impurity element; and irradiating aregion into which the impurity element and the predetermined element areimplanted with light to anneal the region, the light having an emissionintensity distribution, a maximum point of the distribution existing ina wavelength region of not more than 600 nm.

A second aspect of the present invention is a method for manufacturing asemiconductor device comprising: forming a gate insulating film on asemiconductor substrate; forming a gate electrode on the gate insulatingfilm; implanting ions of an impurity element into the semiconductorsubstrate by using at least the gate electrode as a mask; implanting,into the semiconductor substrate, ions of a predetermined element whichis a group IV element or an element having the same conductivity type asthe impurity element and larger in mass number than the impurityelement, by using at least the gate electrode as a mask; and irradiatinga region into which the impurity element and the predetermined elementare implanted with light to anneal the region, the light having anemission intensity distribution, a maximum point of the distributionexisting in a wavelength region of not more than 600 nm.

A third aspect of the present invention is a semiconductor devicecomprising: a first semiconductor region of a first conductivity type;and a second semiconductor region of a second conductivity type formedon the first semiconductor region and containing an impurity element ofthe second conductivity type, wherein the second semiconductor regionincludes at least a portion of a region containing a predeterminedelement which is a group IV element or an element of the secondconductivity type larger in mass number than the impurity element; andthe predetermined element has a density distribution in a depthdirection, and a value of depth of a maximum point of the densitydistribution from a surface of the second semiconductor region issmaller than a value of depth of a boundary between the first and secondsemiconductor regions from the surface of the second semiconductorregion.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A to 1C are sectional views showing a semiconductor devicefabrication method according to the first embodiment of the presentinvention;

FIGS. 2A and 2B are sectional views showing a fabrication method of acomparative example of the first embodiment;

FIG. 3 is a graph showing the density distributions of Ge and B in asemiconductor device obtained by the steps shown in FIGS. 1A to 1C;

FIG. 4 is a graph sowing the density distribution of B in asemiconductor device obtained by the steps shown in FIGS. 2A and 2B;

FIGS. 5A and 5B are graphs showing absorption spectra and reflectionspectra of the silicon substrate surface;

FIG. 6 is a graph showing the emission spectra of a Xe flash lamp and Whalogen lamp and an Si absorption characteristic;

FIG. 7 is a graph showing the relationship between the irradiationenergy density and the sheet resistance;

FIG. 8 is a graph showing the relationship between the Ge accelerationenergy and the sheet resistance;

FIG. 9 is a graph showing the relationship between the Ge accelerationenergy and the junction leakage current;

FIGS. 10A to 10C are sectional views showing a semiconductor devicefabrication method according to the second embodiment of the presentinvention;

FIG. 11 is a graph showing the density distributions of Ge and B in asemiconductor device obtained by the steps shown in FIGS. 10A to 10C;

FIGS. 12A to 12C are sectional views showing a semiconductor devicefabrication method according to the third embodiment of the presentinvention;

FIG. 13 is a graph showing the density distributions of Ge and B in asemiconductor device obtained by the steps shown in FIGS. 12A to 12C;

FIGS. 14A to 14F are sectional views showing a semiconductor devicefabrication method according to the fourth embodiment of the presentinvention;

FIGS. 15A to 15F are sectional views showing a semiconductor devicefabrication method according to the fifth embodiment of the presentinvention;

FIGS. 16A to 16F are sectional views showing a semiconductor devicefabrication method according to the sixth embodiment of the presentinvention; and

FIGS. 17A to 17E are sectional views showing a semiconductor devicefabrication method according to the seventh embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described with reference tothe accompanying drawing.

First Embodiment

FIGS. 1A to 1C are sectional views showing a semiconductor devicefabrication method according to the first embodiment of the presentinvention. This method will be explained by taking the fabrication stepsof a p-type MOS transistor as an example.

First, as shown in FIG. 1A, in accordance with the conventional p-typeMOS transistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3.

Next, as shown in FIG. 1B, the gate electrode 4 is used as a mask toimplant germanium (Ge) ions into the surface region of the n-typesilicon substrate 1. The conditions of this ion implantation are anacceleration energy of 15 keV and a dose of 5×10¹⁴ cm⁻². By this ionimplantation, crystal defect regions 5 are formed in the surface of thesilicon substrate 1. For example, amorphous crystal defect regions 5 areformed. The depth of an end portion of this crystal defect region 5 isabout 20 nm from the surface of the silicon substrate 1.

By using the gate electrode 4 as a mask, boron (B) ions are implantedinto the surface region of the silicon substrate 1. The ion implantationconditions are an acceleration energy of 0.2 keV and a dose of 1×10¹⁵cm⁻². By this ion implantation, impurity regions 6 are formed at theupper portions of the crystal defect regions 5 so as to overlap thesecrystal defect regions 5.

Subsequently, as shown in FIG. 1C, a xenon (Xe) flash lamp is used toirradiate the entire substrate surface with light. The irradiation timeis 10 ms or less, and the irradiation energy density is 35 J/cm². Thislight irradiation (flash lamp anneal) activates the impurity elementsand recovers defects in the crystal defect regions 5 and the impurityregions 6. Consequently, p-type source•drain diffusion layers 7 areobtained. Note that before this light irradiation, the substrate isdesirably heated to a temperature of about 400° C.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

FIGS. 2A and 2B are sectional views showing a fabrication method of acomparative example of the first embodiment. In this comparativeexample, no Ge ions are implanted into a silicon substrate 1, and B ionsare implanted under the same conditions as in the above embodiment.After that, xenon flash lamp light is emitted under the same conditionsas in the above embodiment.

FIG. 3 shows the density distributions of Ge and B obtained by the stepsshown in FIGS. 1A to 1C. FIG. 4 shows the density distribution of Bobtained by the steps shown in FIGS. 2A and 2B.

In this embodiment, a depth at which the Ge density is 10¹⁸ cm⁻³ isabout 55 nm, and a depth at which the B density is 10¹⁸ cm⁻³ is about 12nm. In contrast, in the comparative example a depth at which the Bdensity is 10¹⁸ cm⁻³ is about 18 nm. That is, the region in which B isdistributed in this embodiment is shallower than in the comparativeexample. This is so because when ion implantation of Ge larger in mass(mass number) than B is performed, a large amount of crystal defects aregenerated in the substrate surface to result in an amorphous state, andthis suppresses the channeling phenomenon of B.

The sheet resistance of the diffusion layer was measured and found to be7 kΩ/□ in the sample of the comparative example in which no Ge ions wereimplanted, and 510Ω/□ in the sample of this embodiment in which Ge ionswere implanted. This indicates that the resistance of the diffusionlayer significantly lowered. In addition, resistance variations on thesubstrate surface were measured. As a consequence, σ=10% in the sampleof the comparative example and σ<1.5% in the sample of this embodiment,indicating improvement of the uniformity.

As described above, the impurity profile can be accurately controlled bycombining Ge ion implantation and flash lamp anneal. This makes itpossible to form a low-resistance p-type source•drain diffusion layerhaving a shallow junction with a depth of 20 nm or less.

To examine the reasons for the reduction in the resistance of thediffusion layer and for the improvement of the uniformity of thediffusion layer resistance, the optical characteristics of the siliconsubstrate surface was measured. FIG. 5A is a graph showing absorptionspectra of the silicon substrate surface. FIG. 5B is a graph showingreflection spectra of the silicon substrate surface.

Differences in absorption spectra and reflection spectra are smallbetween a Si substrate (bare Si) into which no ions are implanted and asubstrate into which low acceleration B ions are implanted. However, byion implantation of Ge, the absorption coefficient increases by aboutten times at a wavelength region of 400 nm to 700 nm. In the Sisubstrate (bare Si) into which no ions are implanted, peaks are observednear 360 and 260 nm. These peaks are related to critical points E₁(L₃→L₁) and E₂ (X₄→X₁) of a band structure. When Ge is ion-implanted,these two peaks disappear. This indicates that a large amount of crystaldefects are generated in the substrate surface to break the periodicityof the crystal. On the other hand, the Ge ion implantation decreases theabsorption coefficient at a wavelength of 750 nm or more. This isobserved as an increase of the reflectance of FIG. 5B. It is consideredthat these results are caused by the light interference effect at theinterface between the crystal defect layer (amorphous layer) formed bythe Ge ion implantation and the single crystal layer (crystaldefect-less layer).

FIG. 6 shows the emission spectra (emission intensity distributions) ofa Xe flash lamp and W halogen lamp, and the absorption characteristic ofSi. While the emission intensity of the halogen lamp is high at longerwavelengths, the emission intensity of the flash lamp is high in thevisible light region, particularly, in a region of about 250 to 500 nm.Additionally, the light absorptivity of Si is high in the visible lightregion.

From the foregoing, the emission energy is absorbed by silicon moreefficiently when the flash lamp is used than when the halogen lamp isused. In addition, by generating a large amount of crystal defects inthe surface region of a silicon substrate by ion implantation of Ge, theabsorptivity of the silicon substrate surface can be raised in awavelength region in which the emission intensity of the flash lamp ishigh. Accordingly, the heating efficiency can be raised by combining Geion implantation and flash lamp anneal. This makes it possible toefficiently activate an impurity such as B without breaking its profile.

FIG. 7 shows the results of examination of the relationship between theirradiation energy density and the sheet resistance after the step shownin FIG. 1C of this embodiment. A curve (a) indicates the result when aflash lamp from which no ultraviolet light is cut is used; a curve (b)indicates the result when a flash lamp from which ultraviolet light of400 nm or less is cut. A change in the sheet resistance of the impuritydiffusion layer shows that when the ultraviolet light is cut, there is apower loss of about 30%. That is, in common flash lamp irradiation,ultraviolet light effectively heats an Si substrate.

An Si substrate into which B was implanted at 10 keV and 5×10¹⁵ cm⁻² andan Si substrate into which B was implanted under the same conditions asthe first substrate and then Ge was implanted at 1 keV and 5×10¹⁴ cm⁻²were prepared. Flash lamp anneal was performed for these substrates at asubstrate temperature of 400° C. and an irradiation energy density of 35J/cm². Consequently, the sheet resistance of the sample into which onlyB was ion-implanted was 320Ω/□, whereas the sheet resistance of thesample into which both Ge and B were ion-implanted was 100Ω/□. A depthat which the B density was 1×10¹⁸ cm⁻³ was about 150 nm, and depth atwhich the Ge density was 1×10¹⁸ cm⁻³ was about 10 nm. That is, Ge wasnot contained in the whole region containing B. This means that theabove result is different from the effect of the conventionalpre-amorphous formation process or the effect of increasing theactivation ratio of B by the existence of Ge at high density.

Furthermore, to prove the difference from the effect of the existence ofGe at high density, Ge was ion-implanted, annealing was subsequentlyperformed at 550° C. for 1 hr to recover the crystal state, B wassubsequently ion-implanted, and then flash lamp anneal was performed.The sheet resistance of the diffusion layer of this sample was found tobe 7 kΩ/□, i.e., the sheet resistance could not be lowered.

From the foregoing, the sheet resistance of the impurity diffusion layerwas lowered and the uniformity of the sheet resistance was improved byGe ion implantation presumably because Ge made the surface region of theSi substrate amorphous and this improved the recovery of thecrystallinity, and because the heating efficiency by flash lampirradiation was raised due to an increase of the absorption coefficientin the visible light region and an increase of the light reflectance inthe near infrared region by the light interference effect at theinterface between the amorphous layer and the crystal layer.

In this embodiment as described above, the profile of an impurity can beaccurately controlled by combining ion implantation of Ge andirradiation of light for a short time by a flash lamp. Accordingly, ashallow, high-density, low-resistance diffusion layer can be formed.

Second Embodiment

FIGS. 10A to 10C are sectional views showing a semiconductor devicefabrication method according to the second embodiment of the presentinvention. This method will be explained by taking the fabrication stepsof a p-type MOS transistor as an example.

In this embodiment, an ion implantation region (Ge diffusion layer) of G(predetermined element) is shallower than an ion implantation region (Bdiffusion layer) of B (impurity element). More specifically, the densityof Ge is made lower than that of B at the boundary (p-n junctionboundary) between an n-type semiconductor substrate and a p-type Bdiffusion layer. From another viewpoint, a position at which the Gedensity is equal to the B density at the p-n junction boundary ispresent between the surface of a semiconductor substrate and the p-njunction boundary. For example, the B density at the p-n junctionboundary is about 1×10¹⁸ cm³. From still another viewpoint, a positionat which the density distribution of Ge is a maximum is shallower than aposition at which the B density is 1×10¹⁹/cm³.

First, as shown in FIG. 10A, in accordance with the conventional p-typeMOS transistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3.

Next, as shown in FIG. 10B, the gate electrode 4 is used as a mask toion-implant Ge into the surface region of the n-type silicon substrate1. The conditions of this ion implantation are an acceleration energy of1 keV and a dose of 5×10¹⁴ cm⁻². By this ion implantation, crystaldefect regions 5 are formed in the surface of the silicon substrate 1.The gate electrode 4 is again used as a mask to ion-implant B into thesurface region of the silicon substrate 1. The ion implantationconditions are an acceleration energy of 0.2 keV and a dose of 1×10¹⁵cm⁻². By this ion implantation, impurity regions 6 are formed below thecrystal defect regions 5 so as to overlap these crystal defect regions5.

Subsequently, as shown in FIG. 10C, a xenon (Xe) flash lamp is used toirradiate the entire substrate surface with light. The irradiation timeis 10 ms or less, and the irradiation energy density is 35 J/cm². Thislight irradiation (flash lamp anneal) activates the impurity elementsand recovers defects in the crystal defect regions 5 and the impurityregions 6. Consequently, p-type source•drain diffusion layers 7 areobtained. Note that before this light irradiation, the substrate isdesirably heated to a temperature of about 400° C.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

FIG. 11 shows the density distributions of Ge and B obtained by thesteps shown in FIGS. 10A to 10C. In this embodiment, a depth at whichthe Ge density is 10¹⁸ cm⁻³ is about 10 nm, and a depth at which the Bdensity is 10¹⁸ cm⁻³ is about 14 nm. That is, Ge is not distributed inthe whole impurity region into which B is implanted; the Ge diffusionlayer is formed to be shallower than the B diffusion layer.

The sheet resistance of the diffusion layer was measured and found to be960Ω/□, much lower than when no Ge was implanted. This means that thisresult is different from the effect of the conventional pre-amorphousformation process or the effect of increasing the activation ratio of Bby the existence of Ge at high density.

The junction leakage current was also measured. Consequently, while thejunction leakage current was 2×10⁻¹² A/μm² in the first embodiment, thejunction leakage current was 6×10⁻¹⁷ A/μm² in this embodiment,indicating that the p-n junction characteristics greatly improved. Thisis probably because the Ge diffusion layer was formed in a regionshallower than the B diffusion layer, so no crystal defects caused by Gewere present in a depletion layer. Also, if crystal defects are formedin a region deeper than the B diffusion layer, diffusion of B may beinduced in the annealing step performed later, and this may deterioratethe transistor characteristics. In this embodiment, however, diffusionof B like this can be suppressed.

In this embodiment as described above, the same effects as in the firstembodiment can be obtained. In addition, since the Ge diffusion layer ismade shallower than the B diffusion layer, it is possible to reduce theleakage current and suppress B diffusion. Accordingly, fine transistorssuperior in characteristics and reliability can be obtained.

FIGS. 8 and 9 show the relationship between the Ge ion implantationacceleration condition (the dose is 5×10¹⁴ cm⁻²) and the sheetresistance and the relationship between the Ge ion implantationacceleration energy and the p-n junction leakage current, respectively,when an Si substrate into which B is implanted at an acceleration energyof 0.2 to 0.5 keV and a dose of 1×10¹⁵ cm⁻² is subjected to flash lampanneal at a substrate temperature of 400° C. and an irradiation energydensity of 35 J/cm².

As shown in FIG. 8, the sheet resistance lowers as the Ge accelerationenergy increases. For example, when the B acceleration energy is 0.2keV, a sheet resistance of 1,000Ω/□ can be obtained if Ge is implantedat an acceleration energy of 0.8 keV or more; when the B accelerationenergy is 0.5 keV, a sheet resistance of 1,000Ω/□ can be obtained if Geis implanted at an acceleration energy of 0.5 keV or more.

On the other hand, as shown in FIG. 9, the p-n junction leakage currentincreases as the Ge acceleration energy increases. For example, when theB acceleration energy is 0.2 keV, the junction leakage current is 10⁻¹⁶A/μm² or more if the Ge acceleration energy exceeds 4 keV; when the Bacceleration energy is 0.5 keV, the junction leakage current is 10⁻¹⁶A/μm² or more if the Ge acceleration energy exceeds 6 keV.

Accordingly, when the B acceleration energy is 0.2 keV, the Geacceleration energy is preferably 0.8 keV or more and 4 keV or less;when the B acceleration energy is 0.5 keV, the Ge acceleration energy ispreferably 0.5 keV or more and 6 keV or less.

For example, under conditions as described above a position (p-njunction boundary) at which the B density is 10¹⁸ cm⁻³ can be set in therange of a depth of 20 nm or less. In addition, under the aboveconditions the projected range of Ge ion implantation (a maximum pointof the Ge density distribution) can be made shallower than the p-njunction boundary. Also, a value (depth) obtained by adding a standarddeviation of the density distribution to the projected range can be madeshallower than the p-n junction boundary.

In the first and second embodiments described above, after Ge ision-implanted as a group IV element into a silicon substrate (group IVsemiconductor substrate), B is ion-implanted as an impurity element.However, a group IV element can be ion-implanted after an impurityelement is ion-implanted. Also, as a group IV element, Si, Sn, or Pb canbe used instead of Ge. Furthermore, the dose of a group IV element needonly fall within the range in which a certain amount of crystal defectsor more are produced in the surface region of an Si substrate(preferably, within the range in which the surface region of an Sisubstrate is made amorphous). More specifically, the dose of a group IVelement is desirably 1×10¹⁴ cm⁻² or more and 1×10¹⁶ cm⁻² or less.

In each of the above first and second embodiments, a p-channel MOS (MIS)FET is explained. However, a similar method can also be applied to ann-channel MOS (MIS) FET. In this case, phosphorus (P) or arsenic (As) isused as an n-type impurity to be implanted into a p-type siliconsubstrate. When RTA (Rapid Thermal Anneal) using a halogen lamp as aheating source is performed for an n-type impurity, as the Ge additionamount increases the carrier density decreases and the resistance of thediffusion layer increases. Since the heating efficiency can be increasedby the use of flash lamp anneal, the resistance of the diffusion layercan be effectively lowered.

Third Embodiment

FIGS. 12A to 12C are sectional views showing a semiconductor devicefabrication method according to the third embodiment of the presentinvention. This method will be explained by taking the fabrication stepsof a p-type MOS transistor as an example.

In this embodiment, Ga is used instead of Ge as an element for formingcrystal defect regions 5. Additionally, an ion implantation region (Gadiffusion layer) of Ga (predetermined element) is shallower than an ionimplantation region (B diffusion layer) of B (impurity element).

First, as shown in FIG. 12A, in accordance with the conventional p-typeMOS transistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3.

Next, as shown in FIG. 12B, the gate electrode 4 is used as a mask toion-implant Ga into the surface region of the n-type silicon substrate1. The conditions of this ion implantation are an acceleration energy of1 keV and a dose of 5×10¹⁴ cm⁻². By this ion implantation, crystaldefect regions 5, e.g., amorphous regions, are formed in the surface ofthe silicon substrate 1. The gate electrode 4 is again used as a mask toion-implant B into the surface region of the silicon substrate 1. Theion implantation conditions are an acceleration energy of 0.2 keV and adose of 1×10¹⁵ cm⁻². By this ion implantation, impurity regions 6 areformed below the crystal defect regions 5 so as to overlap these crystaldefect regions 5.

Subsequently, as shown in FIG. 12C, a xenon (Xe) flash lamp is used toirradiate the entire substrate surface with light. The irradiation timeis 10 ms or less, and the irradiation energy density is 35 J/cm². Thislight irradiation (flash lamp anneal) activates the impurity elementsand recovers defects in the crystal defect regions 5 and the impurityregions 6. Consequently, p-type source•drain diffusion layers 7 areobtained. Note that before this light irradiation, the substrate isdesirably heated to a temperature of about 400° C.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

FIG. 13 shows the density distributions of Ga and B obtained by thesteps shown in FIGS. 12A to 12C. In this embodiment, a depth at whichthe Ga density is 10¹⁸ cm⁻³ is about 11 nm, and a depth at which the Bdensity is 10¹⁸ cm⁻³ is about 14 nm. That is, Ga is not distributed inthe whole impurity region into which B is implanted; the Ga diffusionlayer is formed to be shallower than the B diffusion layer.

The sheet resistance of the diffusion layer was measured and found to be850Ω/□. This sheet resistance is lower than that in the secondembodiment because Ga having the same conductivity type as B isactivated. When the junction leakage current was measured, no leakagecurrent increase was found. That is, the ion implantation of Ga did notdeteriorate the p-n junction characteristics.

In this embodiment as described above, the same effects as in the firstembodiment can be obtained. In addition, since the Ga diffusion layer ismade shallower than the B diffusion layer as in the second embodiment,it is possible to reduce the leakage current and suppress B diffusion.Accordingly, fine transistors superior in characteristics andreliability can be obtained.

In the third embodiment described above, B (impurity element) ision-implanted after Ga (group III element) which is in the same group asB is ion-implanted. However, a group III element can be ion-implantedafter an impurity element is ion-implanted. As a group III element, anelement heavier (larger in mass number) than an impurity element can beused. That is, In (indium) or Tl (thallium) can be used instead of Ga.Furthermore, the dose of a group III element need only fall within therange in which a certain amount of crystal defects or more are producedin the surface region of an Si substrate (preferably, within the rangein which the surface region of an Si substrate is made amorphous). Morespecifically, the dose of a group III element is desirably 1×10¹⁴ cm⁻²or more and 1×10¹⁶ cm⁻² or less.

In the above third embodiment, a p-channel MOS (MIS) FET is explained.However, a similar method can also be applied to an n-channel MOS (MIS)FET. In this case, phosphorus (P) or arsenic (As) is used as an n-typeimpurity to be implanted into a p-type silicon substrate. In this case,as an element (group V element) which is in the same group as phosphorusand arsenic, Sb or Bi heavier (larger in mass number) than phosphorusand arsenic can be used.

In the first to third embodiments explained above, the flash lampannealing conditions are an irradiation energy density of 35 J/cm² and asubstrate temperature of 400° C. However, the substrate temperature canbe changed over the range of 200 to 550° C., and the irradiation energydensity can be changed over the range of 10 to 60 J/cm². The substratetemperature is 550° C. or less in order to prevent recovery of thecrystal defect regions before flash lamp irradiation. The irradiationenergy density is 60 J/cm² or less in order to prevent an increase inthe thermal stress by excessive and abrupt irradiation energy, therebypreventing damage such as slips or cracks in an Si substrate. Thesubstrate temperature is 200° C. or more because if the substratetemperature is less than 200° C., irradiation energy exceeding 60 J/cm²is required to activate impurities. As a substrate preheating method,lamp heating using a halogen lamp or the like or heater heating using ahot plate or the like can be used.

In each of the above first to third embodiments, the formation ofshallow source•drain diffusion layers, i.e., the formation of extensionregions is explained. However, the aforementioned method is alsoapplicable to the formation of deep source•drain diffusion layers,polysilicon gate electrodes, or channel regions.

Also, in each of the above first to third embodiments, annealing using aflash lamp as a light source is explained. However, a light source otherthan a flash lamp is also usable provided that a maximum point of theemission intensity distribution of the light is 600 nm or less(preferably, 500 nm or less). The emission period is desirably 100 msecor less, and more desirably, 10 msec or less. An excimer laser can beused as a light source other than a flash lamp.

Fourth Embodiment

FIGS. 14A to 14F are sectional views showing a semiconductor devicefabrication method according to the fourth embodiment of the presentinvention. This embodiment relates to a MOS transistor fabricationmethod using the methods of the first to third embodiments describedabove. Basically, therefore, the various items explained in the first tothird embodiments are properly applicable (this similarly applies to thefifth to seventh embodiments).

First, as shown in FIG. 14A, in accordance with the conventional MOStransistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3.

Next, as shown in FIG. 14B, the gate electrode 4 is used as a mask toion-implant Ge into the surface region of the silicon substrate 1. Theconditions of this ion implantation are an acceleration energy of 1 keVand a dose of 5×10¹⁴ cm⁻². By this ion implantation, crystal defectregions 5 are formed from the surface of the silicon substrate 1 to adepth of 10 nm. The gate electrode 4 is again used as a mask toion-implant B into the surface region of the silicon substrate 1. Theion implantation conditions are an acceleration energy of 0.2 keV and adose of 1×10¹⁵ cm⁻². By this ion implantation, impurity regions 6 are soformed as to overlap the crystal defect regions 5.

Subsequently, as shown in FIG. 14C, the entire substrate surface isirradiated with light of a Xe flash lamp, while the substrate is heatedto a temperature of about 400° C. The irradiation time is 10 ms or less,and the irradiation energy density is 35 J/cm². This light irradiationactivates the impurity elements and recovers defects in the crystaldefect regions 5 and the impurity regions 6. Consequently, shallowsource•drain diffusion layers 7 (extension regions) adjacent to the gateelectrode 4 are obtained.

As shown in FIG. 14D, a silicon nitride film (SiN film) and a siliconoxide film (SiO₂ film) are deposited in this order by CVD. Subsequently,RIE is used to selectively leave the silicon nitride film 8 and thesilicon oxide film 9 on the side walls of the gate electrode 4, therebyforming side wall spacers having a multilayered structure.

As shown in FIGS. 14E, B is ion-implanted by using the gate electrode 4and the side wall spacers including the silicon nitride film 8 and thesilicon oxide film 9 as masks. The ion implantation conditions are anacceleration energy of 5 keV and a dose of 3×10¹⁵ cm⁻². By this ionimplantation, deep impurity regions 10 separated from the end portionsof the gate electrode 4 are formed. This ion implantation also implantsB into the gate electrode (polysilicon).

Next, as shown in FIG. 14F, the entire substrate surface is irradiatedwith light of the Xe flash lamp, while the substrate is heated to atemperature of about 400° C. The irradiation time is 10 ms or less, andthe irradiation energy density is 35 J/cm². This light irradiationactivates the ion-implanted impurity elements and recovers defects inthe impurity regions 10 and the like. Consequently, deep source•draindiffusion layers 11 separated from the end portions of the gateelectrode 4 are obtained.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

In this embodiment, the use of flash lamp anneal can shorten the thermalannealing time for activating the shallow impurity regions 6 adjacent tothe gate electrode 4. This minimizes diffusion of impurities to aportion below the gate electrode and suppresses the short channeleffect. In addition, the heating efficiency rises because crystal defectregions are formed in the surface region of an Si substrate by ionimplantation of Ge before flash lamp light irradiation. Accordingly, theresistance of the diffusion layer can be effectively lowered, and thisimproves the electric current driving capability of a MOS transistor.

Fifth Embodiment

FIGS. 15A to 15F are sectional views showing a semiconductor devicefabrication method according to the fifth embodiment of the presentinvention. This embodiment also relates to a MOS transistor fabricationmethod using the methods of the first to third embodiments describedabove.

First, as shown in FIG. 15A, in accordance with the conventional MOStransistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3.

Next, as shown in FIG. 15B, the gate electrode 4 is used as a mask toion-implant B into the surface region of the silicon substrate 1. Theconditions of this ion implantation are an acceleration energy of 0.2keV and a dose of 1×10¹⁵ cm⁻². By this ion implantation, impurityregions 6 are formed.

Subsequently, as shown in FIG. 15C, RTA using a halogen lamp isperformed. The annealing conditions are a substrate temperature of 800°C. and a heating time of 10 sec. This annealing activates the impurityelement and recovers defects in the impurity regions 6. Consequently,shallow source•drain diffusion layers 7 (extension regions) adjacent tothe gate electrode 4 are obtained.

As shown in FIG. 15D, a silicon nitride film (SiN film) and a siliconoxide film (SiO₂ film) are deposited in this order by CVD. Subsequently,RIE is used to selectively leave the silicon nitride film 8 and thesilicon oxide film 9 on the side walls of the gate electrode 4, therebyforming side wall spacers having a multilayered structure.

As shown in FIG. 15E, Ge is ion-implanted by using the gate electrode 4and the side wall spacers including the silicon nitride film 8 and thesilicon oxide film 9 as masks. The ion implantation conditions are anacceleration energy of 15 keV and a dose of 5×10¹⁴ cm⁻². By this ionimplantation, amorphous regions (crystal defect regions 5) are formedfrom the surface of the silicon substrate 1 to a depth of 20 nm. Afterthat, B is ion-implanted by using the gate electrode and the side wallspacers as masks. The ion implantation conditions are an accelerationenergy of 5 keV and a dose of 3×10¹⁵ cm⁻². By this ion implantation,deep impurity regions 10 separated from the end portions of the gateelectrode 4 are formed. This ion implantation also implants B into thegate electrode (polysilicon).

Next, as shown in FIG. 15F, the entire substrate surface is irradiatedwith light of the Xe flash lamp, while the substrate is heated to atemperature of about 400° C. The irradiation time is 10 ms or less, andthe irradiation energy density is 35 J/cm². This light irradiationactivates the ion-implanted impurity elements and recovers crystaldefects in the impurity regions 10 and the like. Consequently, deepsource•drain diffusion layers 11 separated from the end portions of thegate electrode 4 are obtained.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

In this embodiment, the shallow impurity diffusion layers 7 are exposedto a high temperature only in the flash lamp annealing step foractivating the deep impurity regions 10. This minimizes diffusion ofimpurities to a portion below the gate electrode and suppresses theshort channel effect. In addition, since the number of times of flashlamp irradiation reduces, the generation of thermal stress caused by anabrupt temperature rise can be suppressed. This can reduce substratedamage and improve the yield. Also, the surface region of an Sisubstrate is made amorphous by Ge ion implantation before flash lampirradiation. This improves the recovery of crystallinity and raises theheating efficiency. Accordingly, the resistance of the diffusion layercan be effectively lowered, and this improves the electric currentdriving capability of a MOS transistor.

Sixth Embodiment

FIGS. 16A to 16F are sectional views showing a semiconductor devicefabrication method according to the sixth embodiment of the presentinvention. This embodiment also relates to a MOS transistor fabricationmethod using the methods of the first to third embodiments describedabove.

First, as shown in FIG. 16A, in accordance with the conventional MOStransistor fabrication method, isolation regions 2 are formed in ann-type silicon (Si) substrate 1. After that, a gate insulating film(silicon oxide film) 3 is formed, and a gate electrode 4 is formed onthis gate insulating film 3. A silicon nitride film (SiN film) and asilicon oxide film (SiO₂ film) are deposited in this order by CVD.Subsequently, RIE is used to selectively leave the silicon nitride film8 and the silicon oxide film 9 on the side walls of the gate electrode4, thereby forming side wall spacers having a multilayered structure.

Next, as shown in FIG. 16B, the gate electrode 4 and the side wallspacers are used as masks to ion-implant B. The conditions of this ionimplantation are an acceleration energy of 5 keV and a dose of 3×10¹⁵cm⁻². By this ion implantation, deep impurity regions 10 separated fromthe end portions of the gate electrode 4 are formed. This ionimplantation also implants B into the gate electrode (polysilicon).

Subsequently, as shown in FIG. 16C, RTA using a halogen lamp isperformed. The annealing conditions are a substrate temperature of1,015° C. and a heating time of 10 sec. This annealing activates theimpurity element and recovers defects in the impurity regions 10.Consequently, deep source•drain diffusion layers 11 separated from thegate electrode 4 are obtained.

As shown in FIG. 16D, the silicon oxide film 9 forming a part of theside wall spacers is selectively etched by hydrofluoric acid (HF).

As shown in FIG. 16E, Ge is ion-implanted by using the gate electrode 4and the silicon nitride film 8 as masks. The ion implantation conditionsare an acceleration energy of 1 keV and a dose of 5×10¹⁴ cm⁻². By thision implantation, crystal defect regions 5 are formed from the surfaceof the silicon substrate 1 to a depth of 10 nm. After that, B ision-implanted by using the gate electrode 4 and the silicon nitride film8 as masks. The ion implantation conditions are an acceleration energyof 0.2 keV and a dose of 1×10¹⁵ cm⁻². By this ion implantation, shallowimpurity regions 6 adjacent to the end portions of the gate electrode 4are formed.

Next, as shown in FIG. 16F, the entire substrate surface is irradiatedwith light of the Xe flash lamp, while the substrate is heated to atemperature of about 400° C. The irradiation time is 10 ms or less, andthe irradiation energy density is 35 J/cm². This light irradiationactivates the ion-implanted impurity elements and recovers crystaldefects in the impurity regions 6 and the like. Consequently, shallowsource•drain diffusion layers 7 adjacent to the gate electrode 4 areobtained.

Although the subsequent steps are not shown, a silicon oxide film isformed as an interlayer insulating film on the entire surface at a filmformation temperature of 400° C. by, e.g., atmospheric CVD. After that,contact holes are formed in the interlayer insulating film, andsource•drain electrodes, a gate electrode, interconnections and the likeare formed.

In this embodiment, the shallow source•drain diffusion layers 7 areformed after the deep source•drain diffusion layers 11 are formed.Therefore, the shallow impurity regions 6 are not exposed to the hightemperature of the order of seconds for activating the deep impurityregions 10. This minimizes diffusion of impurities to a portion belowthe gate electrode and suppresses the short channel effect. In addition,since the number of times of flash lamp irradiation reduces, thegeneration of thermal stress caused by an abrupt temperature rise can besuppressed. This can reduce substrate damage and improve the yield.Also, the heating efficiency rises because crystal defect regions areformed in the surface region of an Si substrate by Ge ion implantationbefore flash lamp light irradiation. Accordingly, the resistance of thediffusion layer can be effectively lowered, and this improves theelectric current driving capability of a MOS transistor.

In each of the fourth to sixth embodiments described above, a p-type MOStransistor is explained as an example. However, the above-mentionedmethod is also applicable to an n-type MOS transistor. In addition,various changes as explained in the first to third embodiments can bemade.

Seventh Embodiment

FIGS. 17A to 17E are sectional views showing a semiconductor devicefabrication method according to the seventh embodiment of the presentinvention.

First, as shown in FIG. 17A, a 200-nm thick silicon oxide film (SiO₂film) 22 is deposited on an n-type silicon substrate 21 by CVD. Next, asshown in FIG. 17B, this silicon oxide film 22 is patterned to open a 0.3μm×0.3 μm contact hole 23.

As shown in FIG. 17C, the silicon oxide film 22 is used as a mask toion-implant Ge into the surface region of the silicon substrate 21. Theion implantation conditions are an acceleration energy of 15 keV and adose of 5×10¹⁴ cm⁻². By this ion implantation, a crystal defect region24, e.g., an amorphous region, is formed in the surface of the siliconsubstrate 21. The silicon oxide film 22 is again used as a mask toion-implant B into the surface region of the silicon substrate 21. Theion implantation conditions are an acceleration energy of 5 keV and adose of 5×10¹⁵ cm⁻². By this ion implantation, an impurity region 25 isformed below the crystal defect region 24 so as to overlap this crystaldefect region 24.

As shown in FIG. 17D, a metal film 26 having a thickness of 30 nm orless is formed on the entire surface. This metal film 26 is desirablymade of a metal such as Ti capable of reducing a native oxide film onthe silicon substrate. Generally, it is possible to use group IIIa, IVa,and Va refractory metals.

Subsequently, the entire substrate surface is irradiated with light of aXe flash lamp while the substrate is heated to a temperature of about400° C. The irradiation time is 10 ms or less, and the irradiationenergy density is 35 J/cm². This light irradiation (flash lamp anneal)activates the impurity elements and recovers defects in the crystaldefect region 24 and the impurity region 25, forming a diffusion layer27. Also, by this flash lamp anneal, an excellent ohmic contact can beobtained between the metal film 26 and the diffusion layer 27.

As shown in FIG. 17E, an Al film (film thickness=400 nm), for example,is deposited as a low-resistivity metal film 28. In addition, the metalfilms 26 and 28 are patterned to form an electrode.

The contact resistance between the Al electrode 28 and the siliconsubstrate 21 obtained by the above steps was measured and found to be6×10⁻⁸ Ωcm². In contrast, in a sample of a comparative example obtainedby ion-implanting only B without ion-implanting Ge, the contactresistance was 3×10⁻⁷ Ωcm². These results indicate that in thisembodiment the contact resistance is significantly reduced compared to acomparative example.

Generally, when a metal and a semiconductor are in contact, a barrierlayer exists in the semiconductor to generate a contact resistance. Bygenerating crystal defects in the substrate surface (i.e., by making thesubstrate surface amorphous) by ion implantation of Ge, a localizedlevel can be formed in the barrier layer. Accordingly, carriers readilymove via this localized level formed in the barrier, without exceedingthe barrier like a thermionic emission current. In this embodiment,therefore, the contact resistance significantly lowers presumablybecause a recombination ohmic contact is formed.

In the above embodiment, the Ge (predetermined element) ion implantationstep, B (impurity element) ion implantation step, and metal film(conductive film) 26 formation step can be performed in an arbitraryorder.

In this embodiment as described above, it is possible to obtain ashallow, low-resistance diffusion layer and an excellent ohmic contact.

Note that various changes as described in the first to third embodimentscan also be made in this embodiment. For example, in this embodiment ap-type diffusion layer is formed by ion-implanting boron (B). However,an n-type diffusion layer can also be formed by ion-implantingphosphorus (P) or arsenic (As). Additionally, Si, Sn, or Pb can beion-implanted as a group IV element instead of Ge. To form a p-typediffusion layer, Ga, In, or Tl as a group III element can beion-implanted instead of Ge. Furthermore, to form an n-type diffusionlayer, Sb or Bi as a group V element can be ion-implanted instead of Ge.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit and scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1.-17. (canceled)
 18. A method for manufacturing a semiconductor devicecomprising: implanting ions of an impurity element into a semiconductorregion; implanting, into the semiconductor region, ions of apredetermined element which is a group IV element or an element havingthe same conductivity type as the impurity element and larger in massnumber than the impurity element; and annealing an amorphous region intowhich the ions of the impurity element and the predetermined element areimplanted by irradiating the amorphous region with light of a flash lampto activate the implanted ions of the impurity element and form animpurity diffusion layer containing the activated implanted ions;wherein annealing the amorphous region by irradiating the amorphousregion with the light of the flash lamp is performed with thesemiconductor region preheated under a condition that an amorphous stateof the amorphous region is maintained.
 19. The method according to claim18, further comprising forming a conductive film on the semiconductorregion before annealing the amorphous region.
 20. The method accordingto claim 18, wherein the predetermined element is Si, Ge, Sn, Pb, Ga,In, Tl, Sb, or Bi.
 21. The method according to claim 18, wherein anemission period of the light is not more than 100 msec.
 22. The methodaccording to claim 18, wherein an irradiation energy density of thelight is not less than 10 J/cm² and not more than 60 J/cm².
 23. A methodfor manufacturing a semiconductor device comprising: forming a gateinsulating film on a semiconductor substrate; forming a gate electrodeon the gate insulating film; implanting ions of an impurity element intothe semiconductor substrate by using at least the gate electrode as amask; implanting, into the semiconductor substrate, ions of apredetermined element which is a group IV element or an element havingthe same conductivity type as the impurity element and larger in massnumber than the impurity element, by using at least the gate electrodeas a mask; and annealing an amorphous region into which the ions of theimpurity element and the predetermined element are implanted byirradiating the amorphous region with light of a flash lamp to activatethe implanted ions of the impurity element to form an impurity diffusionlayer containing the activated implanted ions; wherein annealing theamorphous region by irradiating the amorphous region with the light ofthe flash lamp is performed with the semiconductor substrate preheatedunder a condition that an amorphous state of the amorphous region ismaintained.
 24. The method according to claim 23, wherein thepredetermined element is Si, Ge, Sn, Pb, Ga, In, Tl, Sb, or Bi.
 25. Themethod according to claim 23, wherein an emission period of the light isnot more than 100 msec.
 26. The method according to claim 23, wherein anirradiation energy density of the light is not less than 10 J/cm² andnot more than 60 J/cm².